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authorOri Bernstein <ori@eigenstate.org>2013-01-25 19:59:26 -0500
committerOri Bernstein <ori@eigenstate.org>2013-01-25 19:59:26 -0500
commit7baf0c3ce683e750beb30b41cdd7fc2060efbe3f (patch)
tree0b8026602d3f71b6ce5504ca940da17548a9d061
parent3a45cf391fee2805331c88d6947f3bdbd8689478 (diff)
downloadmc-7baf0c3ce683e750beb30b41cdd7fc2060efbe3f.tar.gz
Rename registers for consistency.
The name of the numbered registers are %rNUM, not %NUM.
-rw-r--r--6/locs.c64
-rw-r--r--6/ra.c80
-rw-r--r--6/regs.def64
3 files changed, 104 insertions, 104 deletions
diff --git a/6/locs.c b/6/locs.c
index c68c121..2219658 100644
--- a/6/locs.c
+++ b/6/locs.c
@@ -199,14 +199,14 @@ Loc *coreg(Reg r, Mode m)
[Rbl] = {Rnone, Rbl, Rbx, Rebx, Rrbx},
[Rsil] = {Rnone, Rsil, Rsi, Resi, Rrsi},
[Rdil] = {Rnone, Rdil, Rdi, Redi, Rrdi},
- [R8b] = {Rnone, R8b, R8w, R8d, R8},
- [R9b] = {Rnone, R9b, R9w, R9d, R9},
- [R10b] = {Rnone, R10b, R10w, R10d, R10},
- [R11b] = {Rnone, R11b, R11w, R11d, R11},
- [R12b] = {Rnone, R12b, R12w, R12d, R12},
- [R13b] = {Rnone, R13b, R13w, R13d, R13},
- [R14b] = {Rnone, R14b, R14w, R14d, R14},
- [R15b] = {Rnone, R15b, R15w, R15d, R15},
+ [Rr8b] = {Rnone, Rr8b, Rr8w, Rr8d, Rr8},
+ [Rr9b] = {Rnone, Rr9b, Rr9w, Rr9d, Rr9},
+ [Rr10b] = {Rnone, Rr10b, Rr10w, Rr10d, Rr10},
+ [Rr11b] = {Rnone, Rr11b, Rr11w, Rr11d, Rr11},
+ [Rr12b] = {Rnone, Rr12b, Rr12w, Rr12d, Rr12},
+ [Rr13b] = {Rnone, Rr13b, Rr13w, Rr13d, Rr13},
+ [Rr14b] = {Rnone, Rr14b, Rr14w, Rr14d, Rr14},
+ [Rr15b] = {Rnone, Rr15b, Rr15w, Rr15d, Rr15},
[Rax] = {Rnone, Ral, Rax, Reax, Rrax},
[Rcx] = {Rnone, Rcl, Rcx, Recx, Rrcx},
@@ -214,14 +214,14 @@ Loc *coreg(Reg r, Mode m)
[Rbx] = {Rnone, Rbl, Rbx, Rebx, Rrbx},
[Rsi] = {Rnone, Rsil, Rsi, Resi, Rrsi},
[Rdi] = {Rnone, Rsil, Rdi, Redi, Rrdi},
- [R8w] = {Rnone, R8b, R8w, R8d, R8},
- [R9w] = {Rnone, R9b, R9w, R9d, R9},
- [R10w] = {Rnone, R10b, R10w, R10d, R10},
- [R11w] = {Rnone, R11b, R11w, R11d, R11},
- [R12w] = {Rnone, R12b, R12w, R12d, R12},
- [R13w] = {Rnone, R13b, R13w, R13d, R13},
- [R14w] = {Rnone, R14b, R14w, R14d, R14},
- [R15w] = {Rnone, R15b, R15w, R15d, R15},
+ [Rr8w] = {Rnone, Rr8b, Rr8w, Rr8d, Rr8},
+ [Rr9w] = {Rnone, Rr9b, Rr9w, Rr9d, Rr9},
+ [Rr10w] = {Rnone, Rr10b, Rr10w, Rr10d, Rr10},
+ [Rr11w] = {Rnone, Rr11b, Rr11w, Rr11d, Rr11},
+ [Rr12w] = {Rnone, Rr12b, Rr12w, Rr12d, Rr12},
+ [Rr13w] = {Rnone, Rr13b, Rr13w, Rr13d, Rr13},
+ [Rr14w] = {Rnone, Rr14b, Rr14w, Rr14d, Rr14},
+ [Rr15w] = {Rnone, Rr15b, Rr15w, Rr15d, Rr15},
[Reax] = {Rnone, Ral, Rax, Reax, Rrax},
[Recx] = {Rnone, Rcl, Rcx, Recx, Rrcx},
@@ -229,14 +229,14 @@ Loc *coreg(Reg r, Mode m)
[Rebx] = {Rnone, Rbl, Rbx, Rebx, Rrbx},
[Resi] = {Rnone, Rsil, Rsi, Resi, Rrsi},
[Redi] = {Rnone, Rsil, Rdi, Redi, Rrdi},
- [R8d] = {Rnone, R8b, R8w, R8d, R8},
- [R9d] = {Rnone, R9b, R9w, R9d, R9},
- [R10d] = {Rnone, R10b, R10w, R10d, R10},
- [R11d] = {Rnone, R11b, R11w, R11d, R11},
- [R12d] = {Rnone, R12b, R12w, R12d, R12},
- [R13d] = {Rnone, R13b, R13w, R13d, R13},
- [R14d] = {Rnone, R14b, R14w, R14d, R14},
- [R15d] = {Rnone, R15b, R15w, R15d, R15},
+ [Rr8d] = {Rnone, Rr8b, Rr8w, Rr8d, Rr8},
+ [Rr9d] = {Rnone, Rr9b, Rr9w, Rr9d, Rr9},
+ [Rr10d] = {Rnone, Rr10b, Rr10w, Rr10d, Rr10},
+ [Rr11d] = {Rnone, Rr11b, Rr11w, Rr11d, Rr11},
+ [Rr12d] = {Rnone, Rr12b, Rr12w, Rr12d, Rr12},
+ [Rr13d] = {Rnone, Rr13b, Rr13w, Rr13d, Rr13},
+ [Rr14d] = {Rnone, Rr14b, Rr14w, Rr14d, Rr14},
+ [Rr15d] = {Rnone, Rr15b, Rr15w, Rr15d, Rr15},
[Rrax] = {Rnone, Ral, Rax, Reax, Rrax},
[Rrcx] = {Rnone, Rcl, Rcx, Recx, Rrcx},
@@ -244,14 +244,14 @@ Loc *coreg(Reg r, Mode m)
[Rrbx] = {Rnone, Rbl, Rbx, Rebx, Rrbx},
[Rrsi] = {Rnone, Rsil, Rsi, Resi, Rrsi},
[Rrdi] = {Rnone, Rsil, Rdi, Redi, Rrdi},
- [R8] = {Rnone, R8b, R8w, R8d, R8},
- [R9] = {Rnone, R9b, R9w, R9d, R9},
- [R10] = {Rnone, R10b, R10w, R10d, R10},
- [R11] = {Rnone, R11b, R11w, R11d, R11},
- [R12] = {Rnone, R12b, R12w, R12d, R12},
- [R13] = {Rnone, R13b, R13w, R13d, R13},
- [R14] = {Rnone, R14b, R14w, R14d, R14},
- [R15] = {Rnone, R15b, R15w, R15d, R15},
+ [Rr8] = {Rnone, Rr8b, Rr8w, Rr8d, Rr8},
+ [Rr9] = {Rnone, Rr9b, Rr9w, Rr9d, Rr9},
+ [Rr10] = {Rnone, Rr10b, Rr10w, Rr10d, Rr10},
+ [Rr11] = {Rnone, Rr11b, Rr11w, Rr11d, Rr11},
+ [Rr12] = {Rnone, Rr12b, Rr12w, Rr12d, Rr12},
+ [Rr13] = {Rnone, Rr13b, Rr13w, Rr13d, Rr13},
+ [Rr14] = {Rnone, Rr14b, Rr14w, Rr14d, Rr14},
+ [Rr15] = {Rnone, Rr15b, Rr15w, Rr15d, Rr15},
};
assert(crtab[r][m] != Rnone);
diff --git a/6/ra.c b/6/ra.c
index 2b3cb55..9cc6167 100644
--- a/6/ra.c
+++ b/6/ra.c
@@ -45,14 +45,14 @@ Reg regmap[][Nmode] = {
[3] = {Rnone, Rbl, Rbx, Rebx, Rrbx},
[4] = {Rnone, Rsil, Rsi, Resi, Rrsi},
[5] = {Rnone, Rdil, Rdi, Redi, Rrdi},
- [6] = {Rnone, R8b, R8w, R8d, R8},
- [7] = {Rnone, R9b, R9w, R9d, R9},
- [8] = {Rnone, R10b, R10w, R10d, R10},
- [9] = {Rnone, R11b, R11w, R11d, R11},
- [10] = {Rnone, R12b, R12w, R12d, R12},
- [11] = {Rnone, R13b, R13w, R13d, R13},
- [12] = {Rnone, R14b, R14w, R14d, R14},
- [13] = {Rnone, R15b, R15w, R15d, R15},
+ [6] = {Rnone, Rr8b, Rr8w, Rr8d, Rr8},
+ [7] = {Rnone, Rr9b, Rr9w, Rr9d, Rr9},
+ [8] = {Rnone, Rr10b, Rr10w, Rr10d, Rr10},
+ [9] = {Rnone, Rr11b, Rr11w, Rr11d, Rr11},
+ [10] = {Rnone, Rr12b, Rr12w, Rr12d, Rr12},
+ [11] = {Rnone, Rr13b, Rr13w, Rr13d, Rr13},
+ [12] = {Rnone, Rr14b, Rr14w, Rr14d, Rr14},
+ [13] = {Rnone, Rr15b, Rr15w, Rr15d, Rr15},
};
/* Which regmap entry a register maps to */
@@ -64,14 +64,14 @@ int colourmap[Nreg] = {
[Rbl] = 3,
[Rsil] = 4,
[Rdil] = 5,
- [R8b] = 6,
- [R9b] = 7,
- [R10b] = 8,
- [R11b] = 9,
- [R12b] = 10,
- [R13b] = 11,
- [R14b] = 12,
- [R15b] = 13,
+ [Rr8b] = 6,
+ [Rr9b] = 7,
+ [Rr10b] = 8,
+ [Rr11b] = 9,
+ [Rr12b] = 10,
+ [Rr13b] = 11,
+ [Rr14b] = 12,
+ [Rr15b] = 13,
/* word */
[Rax] = 0,
@@ -80,14 +80,14 @@ int colourmap[Nreg] = {
[Rbx] = 3,
[Rsi] = 4,
[Rdi] = 5,
- [R8w] = 6,
- [R9w] = 7,
- [R10w] = 8,
- [R11w] = 9,
- [R12w] = 10,
- [R13w] = 11,
- [R14w] = 12,
- [R15w] = 13,
+ [Rr8w] = 6,
+ [Rr9w] = 7,
+ [Rr10w] = 8,
+ [Rr11w] = 9,
+ [Rr12w] = 10,
+ [Rr13w] = 11,
+ [Rr14w] = 12,
+ [Rr15w] = 13,
/* dword */
[Reax] = 0,
@@ -96,14 +96,14 @@ int colourmap[Nreg] = {
[Rebx] = 3,
[Resi] = 4,
[Redi] = 5,
- [R8d] = 6,
- [R9d] = 7,
- [R10d] = 8,
- [R11d] = 9,
- [R12d] = 10,
- [R13d] = 11,
- [R14d] = 12,
- [R15d] = 13,
+ [Rr8d] = 6,
+ [Rr9d] = 7,
+ [Rr10d] = 8,
+ [Rr11d] = 9,
+ [Rr12d] = 10,
+ [Rr13d] = 11,
+ [Rr14d] = 12,
+ [Rr15d] = 13,
/* qword */
[Rrax] = 0,
@@ -112,14 +112,14 @@ int colourmap[Nreg] = {
[Rrbx] = 3,
[Rrsi] = 4,
[Rrdi] = 5,
- [R8] = 6,
- [R9] = 7,
- [R10] = 8,
- [R11] = 9,
- [R12] = 10,
- [R13] = 11,
- [R14] = 12,
- [R15] = 13,
+ [Rr8] = 6,
+ [Rr9] = 7,
+ [Rr10] = 8,
+ [Rr11] = 9,
+ [Rr12] = 10,
+ [Rr13] = 11,
+ [Rr14] = 12,
+ [Rr15] = 13,
};
/* %esp, %ebp are not in the allocatable pool */
diff --git a/6/regs.def b/6/regs.def
index 7e481fd..b767d7a 100644
--- a/6/regs.def
+++ b/6/regs.def
@@ -8,14 +8,14 @@ Reg(Rsil, "%sil", ModeB)
Reg(Rdil, "%dil", ModeB)
Reg(Rspl, "%spl", ModeB)
Reg(Rbpl, "%bpl", ModeB)
-Reg(R8b, "%r8b", ModeB)
-Reg(R9b, "%r9b", ModeB)
-Reg(R10b, "%r10b", ModeB)
-Reg(R11b, "%r11b", ModeB)
-Reg(R12b, "%r12b", ModeB)
-Reg(R13b, "%r13b", ModeB)
-Reg(R14b, "%r14b", ModeB)
-Reg(R15b, "%r15b", ModeB)
+Reg(Rr8b, "%r8b", ModeB)
+Reg(Rr9b, "%r9b", ModeB)
+Reg(Rr10b, "%r10b", ModeB)
+Reg(Rr11b, "%r11b", ModeB)
+Reg(Rr12b, "%r12b", ModeB)
+Reg(Rr13b, "%r13b", ModeB)
+Reg(Rr14b, "%r14b", ModeB)
+Reg(Rr15b, "%r15b", ModeB)
/* high byte regs. We *NEVER* allocate these */
Reg(Rah, "%ah", ModeB)
@@ -32,14 +32,14 @@ Reg(Rsi, "%si", ModeW)
Reg(Rdi, "%di", ModeW)
Reg(Rsp, "%sp", ModeW)
Reg(Rbp, "%bp", ModeW)
-Reg(R8w, "%r8w", ModeW)
-Reg(R9w, "%r9w", ModeW)
-Reg(R10w, "%r10w", ModeW)
-Reg(R11w, "%r11w", ModeW)
-Reg(R12w, "%r12w", ModeW)
-Reg(R13w, "%r13w", ModeW)
-Reg(R14w, "%r14w", ModeW)
-Reg(R15w, "%r15w", ModeW)
+Reg(Rr8w, "%r8w", ModeW)
+Reg(Rr9w, "%r9w", ModeW)
+Reg(Rr10w, "%r10w", ModeW)
+Reg(Rr11w, "%r11w", ModeW)
+Reg(Rr12w, "%r12w", ModeW)
+Reg(Rr13w, "%r13w", ModeW)
+Reg(Rr14w, "%r14w", ModeW)
+Reg(Rr15w, "%r15w", ModeW)
/* long regs */
@@ -51,14 +51,14 @@ Reg(Resi, "%esi", ModeL)
Reg(Redi, "%edi", ModeL)
Reg(Resp, "%esp", ModeL)
Reg(Rebp, "%ebp", ModeL)
-Reg(R8d, "%r8d", ModeL)
-Reg(R9d, "%r9d", ModeL)
-Reg(R10d, "%r10d", ModeL)
-Reg(R11d, "%r11d", ModeL)
-Reg(R12d, "%r12d", ModeL)
-Reg(R13d, "%r13d", ModeL)
-Reg(R14d, "%r14d", ModeL)
-Reg(R15d, "%r15d", ModeL)
+Reg(Rr8d, "%r8d", ModeL)
+Reg(Rr9d, "%r9d", ModeL)
+Reg(Rr10d, "%r10d", ModeL)
+Reg(Rr11d, "%r11d", ModeL)
+Reg(Rr12d, "%r12d", ModeL)
+Reg(Rr13d, "%r13d", ModeL)
+Reg(Rr14d, "%r14d", ModeL)
+Reg(Rr15d, "%r15d", ModeL)
/* quad regs */
Reg(Rrax, "%rax", ModeQ)
@@ -69,13 +69,13 @@ Reg(Rrsi, "%rsi", ModeQ)
Reg(Rrdi, "%rdi", ModeQ)
Reg(Rrsp, "%rsp", ModeQ)
Reg(Rrbp, "%rbp", ModeQ)
-Reg(R8, "%r8", ModeQ)
-Reg(R9, "%r9", ModeQ)
-Reg(R10, "%r10", ModeQ)
-Reg(R11, "%r11", ModeQ)
-Reg(R12, "%r12", ModeQ)
-Reg(R13, "%r13", ModeQ)
-Reg(R14, "%r14", ModeQ)
-Reg(R15, "%r15", ModeQ)
+Reg(Rr8, "%r8", ModeQ)
+Reg(Rr9, "%r9", ModeQ)
+Reg(Rr10, "%r10", ModeQ)
+Reg(Rr11, "%r11", ModeQ)
+Reg(Rr12, "%r12", ModeQ)
+Reg(Rr13, "%r13", ModeQ)
+Reg(Rr14, "%r14", ModeQ)
+Reg(Rr15, "%r15", ModeQ)
Reg(Rrip, "%rip", ModeQ)